Electrical parameter controls include:

• The flexibility to assign specific rules to each element in your design. You define the rules required to meet the electrical class characteristics unique to each layer, via type, wire width, or set of wire connections. For example, different vias can be assigned to different nets. Using this feature, a larger via can be used to support the increased current capacity required by power and ground connections. This conserves precious space because only the selected signals use larger vias.
• Improve signal impedance matching by assigning different wire width and clearance rules to different layers. Outer layers generally have higher impedances and are assigned larger wire widths. Inner layers generally have lower impedance and are assigned narrower wire widths to match the impedance of the outer layers. Impedance matching can also be improved by controlling routed nets on certain layer or layer pairs.

Reports include:

• Coupled noise by using the geometric or physical layout of wires and electrical properties of signals carried by the wires. Noise associated with the wires on the same layer and on adjacent layers are considered.
• Uncovers possible timing problems by reporting minimum and maximum wire length violations. The information is reported in a file and graphically displayed.

Automatic Wire Spreading

• Spreads wires to improve the manufacturability of your printed circuit board. It repositions wires to create extra clearance between wires and pins, wires and SMD pads, and adjacent wire segments. You have the flexibility to define a range of spacing values or use default values. Increasing clearances introduces no new conflicts and keeps all vias in place.

Test Point Insertion

• Automatically adds in-circuit testable vias or pads as test points. Testable vias can be probed on the front, back, or both sides of the printed circuit board, thereby supporting both single side and clamshell testers.
• You have the flexibility to select the test point insertion methodology that conforms with your specific manufacturing requirements. Test points can be fixed to avoid costly test fixture modifications. Test point locations can be qualified by specifying test probe surfaces, via sizes, via grids, and minimum center-to-center distance.
• Test point information is graphically displayed and reported in a file, which can then be used as input to your manufacturing test department.

Miter Corners

• Automatically replaces 90-degree corners with a chamfer by using either the default or a user-specified setback value. You can miter corners throughout the entire design or on specific layers.
• You can specify a single value or a range of setback values. It automatically uses the optimum setback within the range, starting from the largest to smallest value.

Buried and Blind Via Control

• Automatically uses blind or buried vias, when required, to transition between layers. You control the clearance between buried vias on different layers as well as the clearance between adjacent vias on the same layer.

Wire Bond Support

• Automatically handles devices that require wire bonding. Bond sites are placed and automatically routed with discrete wires from each site to the pads of a chip mounted on the printed circuit board. You define the type of bond site and the maximum acceptable distance between the component pad and the bond site.

Via and Surface Mount Devices

• Allows you to locate vias within SMD footprints. A via can be placed under an SMD pad at the origin or at the closest grid point nearest the origin. You can also control whether vias placed under SMD pads must fit entirely within the boundary of the pad. If the via shape on the pad layer extends beyond a pad's boundary, the via is not placed.